1. Technical Field
The present disclosure relates to a method of manufacturing a semiconductor device and, more particularly, to a method of manufacturing a semiconductor device, in which upper end portions of internal connection terminals, which are provided to electrode pads of a plurality of semiconductor chips formed on a semiconductor substrate, are electrically connected to wiring patterns.
2. Related Art
FIG. 1 is a sectional view of a semiconductor device in the related art.
By reference to FIG. 1, a semiconductor device 100 (e.g., a chip-size package) in the related art includes a semiconductor chip 101, internal connection terminals 102, a resin layer 103, wiring patterns 104, a solder resist 106, and external connection terminals 107.
The semiconductor chip 101 has a sheet-like semiconductor substrate 110, a semiconductor integrated circuit 111, a plurality of electrode pads 112, and a protection film 113. The semiconductor integrated circuit 111 is provided on the surface side of the semiconductor substrate 110. The semiconductor integrated circuit 111 is composed of a diffusion layer, an insulating layer, vias, wirings, and the like. The plurality of electrode pads 112 are provided on the semiconductor integrated circuit 111. The plurality of electrode pads 112 are connected electrically to the wirings provided on the semiconductor integrated circuit 111. The protection film 113 is provided on the semiconductor integrated circuit 111. The protection film 113 is a film for protecting the semiconductor integrated circuit 111.
The internal connection terminals 102 are provided on the electrode pads 112 respectively. Upper surfaces of upper end portions of the internal connection terminals 102 are exposed from the resin layer 103. The upper end portions of the internal connection terminals 102 are connected to the wiring patterns 104. The resin layer 103 is provided to cover the semiconductor substrate 110 on the side on which the internal connection terminals 102 are provided.
The wiring patterns 104 are provided on the resin layer 103. The wiring patterns 104 are connected to the internal connection terminals 102 respectively. The wiring patterns 104 are connected electrically to the electrode pads 112 via the internal connection terminals 102. The wiring patterns 104 have an external connection terminal providing area 104A, on which the external connection terminal 107 is provided, respectively. The solder resist 106 is provided on the resin layer 103 to cover the wiring patterns 104 except the external connection terminal providing areas 104A.
FIG. 2 to FIG. 10 are views showing steps of manufacturing the semiconductor device in the related art. In FIG. 2 to FIG. 10, the same reference symbols are affixed to the same constituent portions as those of the semiconductor device 100 shown in FIG. 1 in the related art.
At first, in steps shown in FIG. 2, the semiconductor chip 101 having the semiconductor integrated circuit 111, the plurality of electrode pads 112, and the protection film 113 is formed on the surface side of the semiconductor substrate 110. A thinning process is not applied to the semiconductor substrate 110 yet. Then, in steps shown in FIG. 3, the internal connection terminals 102 are formed on the plurality of electrode pads 112 respectively. In this stage, there is variation in height of the plurality of internal connection terminals 102.
Then, in steps shown in FIG. 4, a flat plate 115 is pushed against the upper end portions of the plurality of internal connection terminals 102, and thus respective heights of a plurality of internal connection terminals 102 are set uniformly. Then, in steps shown in FIG. 5, the resin layer 103 is formed to cover the semiconductor chip 101 and the internal connection terminals 102 on the side on which the internal connection terminals 102 are formed.
Then, in steps shown in FIG. 6, the resin layer 103 is polished until upper surfaces 102A of the upper end portions of the internal connection terminals 102 are exposed from the resin layer 103. At this time, the polishing is carried out until an upper surface 103A of the resin layer 103 is almost same level as the upper surfaces 102A of the upper end portions of the internal connection terminals 102.
Then, in steps shown in FIG. 7, the wiring patterns 104 are formed on the upper surface 103A of the resin layer 103. Then, in steps shown in FIG. 8, the solder resist 106 is formed on the resin layer 103 such that this resist covers the wiring patterns 104 except the external connection terminal providing areas 104A.
Then, in steps shown in FIG. 9, the semiconductor substrate 110 is polished from the back surface side to reduce a thickness of the semiconductor substrate 110. Then, in steps shown in FIG. 10, the external connection terminal 107 is formed on the external connection terminal providing areas 104A respectively. As a result, the semiconductor device 100 is manufactured (see e.g., Japanese Patent No. 3614828).
However, in the method of manufacturing the semiconductor device 100 in the related art, the step of making the height of the plurality of internal connection terminals 102 uniform and the step of exposing the upper surfaces 102A of the plurality of internal connection terminals 102 from the resin layer 103 by polishing the resin layer 103 are required. Therefore, such a problem existed that the number of steps is increased and thus a production cost of the semiconductor device 100 is increased.
Also, upon polishing the resin layer 103, it is difficult to remove the resin layer 103 existing on the upper surfaces 102A of the upper end portions of the internal connection terminals 102 with good precision. Therefore, the resin layer 103 still remains on the upper surfaces 102A of the upper end portions of the internal connection terminals 102. As a result, such a problem existed that adhesion between the internal connection terminals 102 and the wiring patterns 104 is degraded (in the worst case, peeling occurs between the internal connection terminals 102 and the wiring patterns 104), a resistance value between the internal connection terminals 102 and the wiring patterns 104 is increased. Thus, the yield of the semiconductor device 100 is lowered.